Context dependent make macros: $<, $@, and $*. The $< macro expands to the file in the dependency list that triggered the rule to fire, the $@ macro expands to the target object that should be built by the rule, and the $* expands to the common stem. Implicit make rule uses these. For example, the implicit rule for building relocatable object files from C source files is:
.c.o: $(CC) $(CFLAGS) -c $<make requires that filenames follow a naming convention. .l files are lex source files (lex is a lexical analyzer generator), .y files are yacc source files (yacc is a compiler compiler which generates parsers for LALR(n) languages [you don't need to know this, but you'll encounter this again when you take compilers]), etc. These are some of the standard suffices that make already know about, and there are implicit rules for doing the .l.o and .y.o conversions.
make strips known suffices off of filenames to match implicit rules. For example, if you had a file pgm.c in your current directory, and your Makefile contained
pgm: pgm.o $(CC) -o pgm pgm.o -lXaw -lXt -lX11and you typed in make pgm, even though no pgm.o exists and there are no explicit rule for creating the pgm.o file, make will know that .o is a known suffix, and to look for an implicit rule that will build pgm.o from a file in the current directory with the right name. Since there are .c.o, .l.o, and .y.o rules (there are actually more), make will look for files named pgm.c, pgm.l, or pgm.y as candidate source files. Since pgm.c exists, make will go ahead and use the .c.o rule to create the needed pgm.o file.
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