CSE 30 -- Lecture 13 -- Nov 18

Pipelines. See chapter 6. Branch delay slot in raw machine code. Load delay; bubbles in the pipe; stalling. Briefly mentioned superscalar, multiple instruction issue architectures. Noted how different pipeline depths would require different numbers of delay slots, so having a branch delay slot exposes a detail of the implementation of the instruction set architecture which should not have been.
[ search CSE | CSE home | bsy's home page | webster i/f | yahoo | hotbot | lycos | altavista | pgp key svr | spam | commerce ]
picture of bsy

bsy+cse30.f99@cs.ucsd.edu, last updated Wed Nov 24 18:44:04 PST 1999. Copyright 1999 Bennet Yee.
email bsy.

Don't make me hand over my privacy keys!