CSE 30 -- Lecture 13 -- Nov 18
Pipelines. See chapter 6. Branch delay slot in raw machine code.
Load delay; bubbles in the pipe; stalling. Briefly mentioned
superscalar, multiple instruction issue architectures. Noted how
different pipeline depths would require different numbers of delay
slots, so having a branch delay slot exposes a detail of the
implementation of the instruction set architecture which should not
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