Self-modifying code is bad

Self-modifying code is generally frowned upon. Not only is it hard to read and debug, it also creates problems with the cache (``cache coherence''). First, what is a cache?

The cache sits between the CPU and the system bus:

Similar to registers, cache memory is fast in comparison to ``main'' memory (but cache is typically a little slower than registers.) Unlike registers, which may be named using only a few bits within instruction words (in parameter fields of an instruction), cache memory is not directly referenced: cache memory holds copies of frequently used data from main memory, and its contents are accessed simply by referring to main memory addresses. Accesses to cache is therefore transparent: a program need not do anything special to make use of the cache.

The purpose of the cache is to provide a faster-to-access copy of what's already in main memory. The hope is that the program has locality: that it will re-access a memory location that it had used many times in a short period of time. This is true for instruction memory holding the body of a small loop, for example, since each time the CPU runs through the loop, the body is re-read. This is also true for some kinds of data memory: for example, variables that were not placed within registers but are still used frequently within one or perhaps several functions.

RISC machines typically will separate out cache memory into two kinds: instruction cache (``I-cache'') and data cache (``D-cache''). The reason for this an optimization one: because the majority of programs do not modify themselves, the RISC architects realize that if they simply forbid self-modifying code, they can make the I-cache be read-only (from the CPU) (the D-cache must, of course, be read-write). By making the I-cache read-only, the circuitry implementing the I-cache is simplified, and the I-cache can be made more dense: the amount of memory per square centimeter of silicon is increased, and the effectiveness of the I-cache improves for the same amount of chip area expended.

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