RISC computers' instruction sets are designed by using quantitative measurements of real programs. The goal is to find out what instructions are important to real programs by examining the instruction trace (instructions actually executed by the CPU, as opposed to static instruction counts from the executable image -- think about the effect of loops), and optimizing the instruction set to make those frequently used instructions fast -- and omit those instructions that are rarely used to make the cycle time, the time to run one instruction, as short as possible. RISC is not about making the instruction set simpler blindly -- it is about making the instruction set as simple as needed, and no simpler. Any omitted instructions must be easily synthesized from a short sequence of RISC instructions: the cost of omitting the complex instructions, in terms of the (infrequent) use of the replacement equivalent sequences of RISC instructions, must be out-weighed by the overall benefit to the design: the shorter cycle time.
The OIC singleton instruction set, in contrast, is very much suboptimal. All real machines include hardware to perform multiplication, for example -- ALUs tend to be able to multiply in a few cycles (like 5 or so) -- and the real mult instruction, making use of this hardware, will run much faster than a synthesized multiplication macro could possibly run.
One interesting thing to note is that the RISC design process necessarily includes a feedback mechanism: most RISCs are designed by instrumenting existing computer programs, and most RISC designers sell computers that run C or C++. So the instruction traces used by the designers tend to be from C programs, and thus, RISC computers tend to run C relatively well. Because RISCs tend to run C well -- and the C compiler is also part of this design feedback cycle -- application writers tend to favor C/C++ over other languages, and when it's time to gather instruction traces for the next-generation RISC chip, the bias can get even more extreme. The operating system used also has a marked effect: the DEC Alpha instruction set includes instructions that make implementing OpenVMS easier/run faster (odd/even test).
bsy@cse.ucsd.edu, last updated